---
title: Altera Launches Agilex 2X FPGA and SoC Portfolio
url: https://www.elseif.net/altera-launches-agilex-2x-fpga-and-soc-portfolio
published: 2026-10-31T16:04:32+00:00
language: en
section: Models
source: https://www.techtalkthai.com/altera-launches-agilex-2x-fpga-soc-portfolio-agilex-27/
organizations: Altera, Arm
publisher: elseif
---

# Altera Launches Agilex 2X FPGA and SoC Portfolio

Altera has introduced the Agilex 2X portfolio of field programmable gate arrays and system on chips, which includes devices ranging from high performance and mid range to power and cost efficient models.

The portfolio is designed to support digital artificial intelligence in infrastructure and physical artificial intelligence at the edge, such as robotics. The new devices build upon existing fabric architecture with improvements to performance per watt, including AI tensor digital signal processing blocks, the latest Arm cores for embedded processing, high bandwidth connectivity, and end to end security systems.

The portfolio consists of four families. Agilex 27 is intended for high processing and bandwidth tasks such as datapath processing, beamforming, and radio frequency processing. Agilex 25 is optimized for low latency sensors, drones, and 4K or 8K video processing. Agilex 23 combines functional safety, real time processing, and embedded compute for industrial automation, robotics, and automotive systems. Agilex 22 focuses on high input output density for motor control, board and rack control, interface bridging, and root of trust.

Agilex 27 is the first family to be released, targeting terabit networks, 6G networks, satellite networks, aerospace and defense, and digital artificial intelligence infrastructure. It utilizes third generation HyperFlex fabric to provide 1.8 times the performance per watt compared to the previous generation. The chip includes a HyperFlow data network for multi terabit per second internal data transfer and supports transceivers up to 256 gigabits per second, PCIe 6.0 and 7.0, and memory interfaces including DDR5, LPDDR5X, and LPDDR6.

Security features for Agilex 27 include a Secure Device Manager acting as a hardware root of trust, which supports anti tamper protections, protected key management, attestation, identity, and secure boot. The chip features datapath encryption for main interfaces at line rate, including PCIe Integrity and Data Encryption, Ethernet MACsec, and Inline Memory Encryption, and includes crypto agility for post quantum cryptography.

All models in the portfolio use the Quartus Prime software and the QuartusIQ artificial intelligence expert companion. They share a common foundation of embedded software, including the Nios V soft processor, Arm based hard processors, and functional safety approaches.

Quartus Prime will support Agilex 27 for early access customers starting in mid November. Engineering samples for Agilex 27 are expected in the second half of 2027. QuartusIQ is available for download in Quartus Prime 26.3 for all Altera field programmable gate arrays supported by the Quartus Prime Pro Edition.