AI data center optical interconnect market to hit $144 billion by 2030, an over ten-fold increase from 2024 figures, according to new projections — silicon photonics expected to account for nearly two-thirds of revenue, driven by co-packaged optics

The optical interconnect market is poised for explosive growth as AI workloads push data center networks beyond the limits of copper-based solutions. Copper’s power consumption and signal loss become unmanageable at speeds exceeding a few hundred gigabits per lane, forcing a transition to photonics. This shift is not optional, it’s a necessity for scaling AI infrastructure. The projected $144 billion market by 2030 reflects the urgency of this transition, with silicon photonics emerging as the dominant technology due to its compatibility with CMOS manufacturing processes.

Silicon photonics offers a cost-effective path to mass-producing photonic integrated circuits (PICs) by leveraging existing semiconductor foundries. However, silicon cannot generate laser light, so laser chips still rely on expensive III-V materials like indium phosphide. This creates a bottleneck: while PICs can be manufactured at scale, lasers remain a separate, heat-sensitive component. Co-packaged optics mitigate this by placing the PIC closer to the compute, reducing electrical signal paths to millimeters, but the laser must still be externally coupled. Recent advancements, such as wafer-level integration of III-V lasers with silicon photonics, aim to address this challenge.

The adoption of co-packaged optics (CPO) is accelerating as AI data centers demand higher bandwidth and lower power consumption. Traditional pluggable transceivers require GPU signals to travel inches across copper traces, consuming significant power at terabit speeds. CPO shrinks this distance by integrating the PIC directly onto the switch or accelerator package. However, this approach introduces thermal management challenges, as the PIC must operate in close proximity to heat-generating compute chips. The industry’s push toward 1.6T and higher speeds will further strain these designs, requiring engineers to balance performance, power efficiency, and thermal constraints.

The market growth is underpinned by substantial investments in photonics, including acquisitions, alliances, and design tool integrations. For example, OpenLight and Tower Semiconductor’s collaboration embeds photonic design kits into mainstream chip-design software, lowering the barrier to entry for 400G and 1.6T chip development. This democratization of design tools will accelerate innovation but also intensify competition. Engineers must navigate a rapidly evolving ecosystem where optical and electrical domains converge, demanding new expertise in photonic integration, signal integrity, and thermal management.