TECH Signal 496
Assembly Hall of Shame
The Assembly Hall of Shame ranks single x86 instructions by their longest observed latency when deliberately stalled via resource contention on a stock system.
Engineers can see which instructions suffer the most from microcode assists, cache-line splits, or uncore traffic, revealing hidden worst-case paths. This insight helps in sizing timing budgets for real-time or safety-critical code and in evaluating the impact of contention-based attacks.
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The current record holder is fxrstor64 loading 512 bytes of FPU/MMX/XMM state from a MMIO region with high latency while other cores saturate the PCIe fabric, scoring ~198 billion cycles (~62 s).
The leaderboard lists many common instructions with their measured worst-case cycles, ranging from a single-cycle nop to operations such as fadd (677 cycles) and mfence (326 cycles).
All measurements are normalized to the CPU base clock, require a factory-stock configuration, and time only a single non-interruptible instruction while other cores generate contention.
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What the cluster adds up to.
The project shifts focus from typical performance optimization to measuring the slowest possible execution of a single instruction. It does this by creating contention on shared resources such as the PCIe fabric or MMIO regions while the target instruction is in flight. The resulting scores reflect worst-case latency under artificial load rather than typical throughput.
The current champion, fxrstor64, loads a large FPU/MMX/XMM state block from a MMIO region that exhibits high latency. Meanwhile, other cores execute tight loops that read a different high-latency MMIO register, generating a flood of non-posted transactions that occupy the PCIe root complex and endpoint. This stalls the load instruction, allowing its latency to grow to hundreds of billions of cycles.
The leaderboard includes a variety of instructions that stress different microarchitectural paths. Simple operations like nop and rdtsc show minimal overhead, while instructions that trigger assists (fldl, fadd, fsin), cause cache-line splits (split lock), or require uncore synchronization (mfence, mov cr3) exhibit significantly higher cycle counts. These numbers expose where microcode assists, divider logic, or TLB invalidation become bottlenecks.
For engineers, the data provide concrete worst-case numbers that can be used in timing analysis for interrupt handlers, control loops, or safety-critical tasks. Replicating the conditions requires a multi-core system, access to MMIO registers with configurable latency, and the ability to generate sustained traffic from other cores. The cost is primarily the setup effort and the temporary degradation of overall system performance during measurement.
The measurements are valid only on factory-stock, non-virtualized hardware where the instructed operation is not trapped or emulated. Results may not apply if the system lacks a PCIe fabric, if the instruction is intercepted by a hypervisor, or if the target instruction is interruptible (e.g., rep movs). Outside these constraints, the observed extreme latencies may not be reproducible.
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