INFRA Signal 160
Jane Street launches ASIC competition for open-source protocol emulator chip design
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Jane Street announced a competition to design an open-source, general-purpose protocol emulator ASIC, with winning designs fabricated on IHP's 130nm process through Tiny Tapeout and winners receiving chips on dev boards.
This gives engineers a funded path to tape out a custom ASIC that implements hardware protocols in firmware rather than fixed logic, similar to the RP2040's PIO or TI's PRU cores. The competition also signals growing industry interest in novel verification methodologies, including formal methods and AI-assisted verification, for ASIC design flows.
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The competition targets IHP's 130nm CMOS5L process with an 8×4 Tiny Tapeout tile budget, yielding approximately 1 mm² of nominal tile area.
Winning designs will be fabricated on the March 2027 CMOS5L shuttle, with winners receiving fabricated chips mounted on dev boards.
Submissions must be open source and are due January 18th, 2027; team participation is recommended.
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