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China's CXMT hits 12nm-class DRAM milestone using quadruple-patterning to boost capacity
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CXMT has begun mass production of its 5th-generation DRAM process, G5, which uses quadruple-patterning lithography to achieve an active-area half-pitch of 11.95nm and increase die capacity by 50% compared to previous generations.
The shift to G5 enables higher wafer density and could reduce per-bit manufacturing costs, but the lack of disclosed yields and performance metrics limits immediate impact assessment. The technology's practical viability depends on overcoming challenges associated with extreme aspect ratios and process maturity.
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CXMT's G5 process uses quadruple-patterning lithography to achieve an active-area half-pitch of 11.95nm, placing it in the 12nm-class DRAM range.
The new process increases die capacity by 50% through denser cell design and modified capacitor structures with a 45:1 aspect ratio.
Mass production of 24Gb LPDDR5X chips based on G5 has begun, targeting integration into Chinese flagship smartphones.
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The reported 12nm-class designation is a simplification, as the actual active-area half-pitch of 11.95nm does not correspond directly to conventional node naming used by competitors like Micron or SK hynix.
While CXMT claims a 50% increase in die capacity, the absence of yield data or productivity metrics prevents assessment of real-world manufacturing gains or cost advantages.
The adoption of a 45:1 aspect ratio for storage capacitors introduces significant process complexity, potentially affecting yield, stability, and long-term reliability despite enabling higher density.
The focus on domestic DRAM advancement reflects strategic goals for semiconductor self-reliance, but technical parity with established players remains unproven without independent validation of performance and yield.
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