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CPython Officially Adds RISC-V Support As a Tier 3 Platform
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CPython now officially supports RISC-V as a Tier 3 platform, allowing the interpreter to be built and run on RISC-V hardware while still permitting occasional breakage that does not block core releases.
The official Tier 3 status reduces integration friction for teams that want to include RISC-V in their CI/CD pipelines by providing upstream CPython support. It also highlights the need for community testing and hardware access to improve stability and eventually reach Tier 2 support.
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CPython's RISC-V support is now listed as a Tier 3 platform in PEP 11 after community-driven testing on real silicon.
The RISE Project supplied hardware that serves as buildbots for automated testing and debugging.
Future goals include moving RISC-V to Tier 2, integrating hardware into continuous integration, and exploiting architecture-specific extensions for performance.
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The Python core development team has added RISC-V support to CPython as a Tier 3 platform. This inclusion follows months of collaborative work to run tests on real silicon and fix architecture-specific bugs. Contributors used hardware supplied by the RISE Project to operate buildbots for automated testing. The change is recorded in PEP 11, the document that lists supported platforms.
Adopting the support requires developers to build and run CPython on RISC-V boards and report any issues. Currently, test execution occurs only after a patch is merged, which delays feedback on defects. The team is working with the RISE Project to place RISC-V hardware directly in the continuous integration pipeline. This effort aims to reduce latency and give contributors faster automated feedback.
As a Tier 3 platform, RISC-V may still experience breakage that does not block core CPython releases. Official upstream support removes a historical friction point for integrating RISC-V into software CI/CD pipelines. However, the platform is not guaranteed to be stable across all configurations or workloads. Users should expect occasional failures and are encouraged to test their own workloads.
Maintainers plan to advance RISC-V toward Tier 2 support within PEP 11. Future work includes exploring architecture-specific optimizations such as vector extensions and bit manipulation. Broader RISC-V viability for Python will depend on contributions from third-party packages, compilers, and toolchains. The team has issued an explicit call for testing from anyone with access to compatible RISC-V hardware.
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