INFRA Signal 252 2 feeds carried it
IBM reveals dual-ISA z/Architecture core with integrated ARM support at Hot Chips 2026
↗
IBM’s next-generation z/Architecture processor core integrates ARM instruction set decoding alongside z/ISA in shared hardware structures
Engineers building or porting workloads to IBM’s z platform can now run ARM-compiled binaries natively without emulation. The design reuses most of the core’s large structures, so the silicon cost is small, but the memory-ordering model remains z’s strong ordering for both ISAs. This may simplify hybrid workloads that span traditional z and ARM-based cloud stacks.
Written by elseif from the cluster below · every claim links back to a sourceThe three things worth knowing
The core shares branch prediction, caches, and register files between z/ISA and ARM decoders
Hardware handles endianness and memory ordering automatically, enforcing z’s strong ordering for both ISAs
Additional transistors for separate decoders and new FP16/BF16 data flows are minor compared to existing structures
THE READ
What the cluster adds up to.
IBM’s next-generation z/Architecture core integrates ARM instruction set decoding directly into the pipeline. The decode stage uses separate decoders for z/ISA and ARM instructions, but shares most of the surrounding structures, branch prediction, caches, and register files. This reuse keeps the silicon overhead low, as the additional transistors for the decoders and new floating-point formats are small relative to the core’s existing large structures.
The core handles endianness and memory ordering in hardware. z/ISA is big-endian, while ARM is bi-endian with a little-endian mode; the load-store unit swaps bytes automatically. Memory ordering is always strongly ordered, matching z’s model, and the ARM TSO feature is effectively a no-op. This simplifies software, as developers do not need to manage endianness or ordering in code, but it may limit performance for workloads optimized for ARM’s weak ordering.
The business rationale appears to be ecosystem compatibility. IBM’s CTO notes the rapid growth of the ARM software ecosystem, suggesting the dual-ISA design aims to attract ARM-based workloads to z hardware. For engineers, this means ARM-compiled binaries can run natively on z, but the core’s strong ordering and hardware-managed endianness may require testing for workloads that assume ARM’s default weak ordering or little-endian mode.
The design stops short of full ISA unification. While the core shares most structures, the decoders remain separate, and the memory model is fixed to z’s strong ordering. This limits the flexibility for workloads that rely on ARM’s weak ordering for performance, but it avoids the complexity of a dynamic memory model. The approach is pragmatic, prioritizing reuse of existing z hardware over full ARM compatibility.
Written by elseif from the cluster below · checked for specifics the sources never containedTHE CLUSTER