Samsung moves HBM base die to 4nm logic node to reduce power and enable on-package memory controllers

Samsung’s decision to fabricate HBM base dies on a 4nm logic node addresses a key bottleneck in memory bandwidth scaling. The base die’s interface with the host compute die has been a persistent area and power constraint, as increasing data pin counts exacerbates both. By switching to a logic process, Samsung mitigates these issues while unlocking unused die area for additional functionality. This shift is not just about efficiency, it creates space for architectural changes that could redefine how memory and compute interact.

The most immediate opportunity is integrating the memory controller onto the HBM base die. Traditionally, DRAM is passive, relying on a host controller to manage low-level operations like row precharging and refresh cycles. Moving these functions onto the base die could reduce PHY area on both the compute and memory sides, but it comes at the cost of compatibility. The standard HBM interface would be replaced with a custom die-to-die protocol, requiring compute dies to support it. This could fragment the ecosystem unless Samsung standardizes the new protocol, which remains uncertain.

Beyond memory controllers, Samsung is exploring other uses for the freed-up base die area. One proposal is an SRAM-based remapping table to handle failed DRAM cells more flexibly than current row/column spares. Another is adding sensors for better telemetry, which could improve thermal and voltage management. A test block for pattern generation could also enhance yield and test coverage. These additions are incremental but could collectively improve reliability and observability in high-performance systems.

More ambitious ideas include memory expansion and in-memory compute. The base die could act as an IO die, interfacing with external memory to increase capacity beyond interposer limits. In-memory compute, however, faces significant challenges. Near-memory processing is inherently NUMA-like, with compute units tied to specific memory regions. Without large caches, data locality becomes a bottleneck, limiting its usefulness to niche applications like data pre-processing. The practicality of these features will depend on how well Samsung can mitigate these constraints.

The long-term implications of this shift are still unclear. If successful, it could reduce system complexity by consolidating memory management onto the HBM stack. However, the need for custom integration may slow adoption, particularly in markets where standardization is critical. The trade-offs between flexibility, power efficiency, and compatibility will determine whether this becomes a niche optimization or a broader industry trend.