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XCENA and Samsung's MX1 packs 3072 RISC-V cores into a CXL memory expander
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XCENA and Samsung's MX1 is a CXL memory expansion card that adds 3072 RISC-V cores and SSD hosting to up to 2 TB of DDR5.
For engineers building memory-hungry ML workloads, MX1 offers a way to attach large DDR5 pools and offload data-parallel processing near memory, reducing host data movement. The device's programming model resembles OpenCL/CUDA, so existing kernel-style code can be adapted, but the reliance on small in-order cores at 1.1 GHz means it suits bandwidth-bound tasks, not latency-sensitive single-threaded work.
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MX1 connects via PCIe 6/CXL 3.2 x8, providing 128 GB/s host bandwidth and hosting up to 2 TB of DDR5.
The card's 3072 RISC-V cores are organized into 24 subsystems, each running an independent job, with a GPU-like cache hierarchy.
XCENA's software shares virtual memory with the host, allowing pointer sharing and kernel launches similar to OpenCL's SVM.
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The MX1 changes the CXL memory expansion landscape by adding a substantial compute block alongside the memory pool. Instead of a passive memory expander, it offers 3072 in-order RISC-V cores running at 1.1 GHz, plus downstream PCIe 6 lanes for SSDs. This lets a host expose a massive memory capacity while offloading data-parallel kernels to the device, directly addressing the memory appetite of ML models.
The architecture is deliberately GPU-like: each core has a 4 KB virtually addressed L1 data cache, and clusters share a 128 KB VIPT L2 data cache with a TLB. Instruction fetches bypass virtual memory entirely, using predefined physical addresses, which simplifies the hardware but forces software to manage code placement. The 24 subsystems act as job units, each running an independent kernel, and the in-house NoC ties them to L3 and memory.
Adopting MX1 means writing kernels in an OpenCL/CUDA style, with mu::getTaskIdx() replacing get_global_id(). The shared virtual memory model lets host and device share pointers, easing data exchange. The cost is that single-threaded performance is minimal, and the 40 W chip power (90 W board) is spent on many weak cores rather than a few strong ones. This is a trade-off that only pays off for highly parallel, bandwidth-saturated workloads.
The design stops working when workloads require low latency, complex control flow, or fine-grained synchronization. The reliance on 64 KB pages for TLB coverage may clash with OS page sizes, and the restriction of the program counter to device physical addresses limits flexibility. Engineers should benchmark their kernels against the subsystem allocation granularity and the 128 GB/s host link to see if the near-memory compute actually reduces data movement enough to justify the programming overhead.
The collaboration with Samsung and the use of a 4nm process suggest a production-ready part, but it is still an add-in card. The real test is whether the software stack can deliver the promised power efficiency without burdening the host. For now, MX1 is a concrete step toward near-memory computing, but it is a specialized tool, not a general-purpose CPU replacement.
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