Presentation links semiconductor supply chain constraints to AI software architecture decisions

The presentation frames AI software architecture as downstream of semiconductor supply-chain physics. Chip fabrication lead times, wafer yields, and packaging constraints determine how many GPUs are available, at what price, and with what performance. These limits propagate into data center planning: power contracts, cooling infrastructure, and rack density must be sized months before hardware arrives. Engineers who assume infinite GPU supply or uniform performance will hit hard walls when scaling models or deploying inference endpoints.

Data center expansion is now a first-order constraint on AI workloads. The talk highlights that power delivery, not just chip supply, dictates where new clusters can be built. Hyperscalers are signing 20-year power purchase agreements and retrofitting older facilities to handle higher rack densities. For engineers, this means latency-sensitive workloads may need to be co-located with specific data centers, and model parallelism strategies must account for inter-GPU bandwidth that varies by region and provider.

Networking bottlenecks emerge as a critical scaling limit. The presentation ties GPU performance benchmarks to real-world system-level metrics, showing that inter-node communication often becomes the bottleneck in distributed training. Engineers must now design for heterogeneous networking topologies, where intra-rack bandwidth differs from inter-rack or cross-data-center bandwidth. This affects model partitioning, gradient synchronization, and even the choice of parallelism strategy (e.g., tensor vs. pipeline parallelism).

Token economics are presented as the end-to-end consequence of these hardware constraints. The cost of inference is not just a function of GPU utilization but also of data center power costs, networking egress fees, and semiconductor fabrication yields. Engineers optimizing for cost-per-token must now consider the entire stack, from wafer fab to model serving. The talk suggests that hardware-aware software design, such as model quantization, sparsity, or dynamic batching, can mitigate some of these constraints, but only if the underlying hardware limitations are understood.