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Samsung Foundry extends SF2 run as 1.4nm slips to 2029, High-NA EUV debuts at 1nm-class
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Samsung Foundry pushes its 1.4nm node to 2029, extending SF2's lifespan, and plans to adopt High-NA EUV for its 1nm-class process in 2030.
For engineers designing chips on Samsung's processes, the extended SF2 lifespan means more time to optimize for that node, but also a longer wait for the 1.4nm node. The planned switch to High-NA EUV at 1nm-class introduces new cost and design constraints, including smaller exposure fields and die stitching for large chips. Understanding these trade-offs is critical for planning future products.
Written by elseif from the cluster below · every claim links back to a sourceThe three things worth knowing
Samsung Foundry delays its 1.4nm node from 2027 to 2029, focusing on refining SF2 processes.
The company plans to adopt High-NA EUV lithography starting with its 1nm-class node in 2030.
High-NA EUV tools bring higher costs, smaller exposure fields, and require new materials and processes.
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Samsung Foundry's updated roadmap moves the 1.4nm node to 2029, a two-year delay from the previous 2027 target. This extends the lifespan of the SF2 family, which now includes multiple variants like SF2P, SF2X, SF2A, and SF2Z with backside power delivery. The company is prioritizing yield and volume improvements on SF2 to satisfy long-term customers like Tesla, which has a supply agreement through 2033. This shift indicates a slower leading-edge cadence in favor of commercial competitiveness.
Samsung plans to use High-NA EUV only for its 1nm-class node in 2030, not for 2nm or 1.4nm. The technology still needs improvements, as stated by a Samsung VP. High-NA EUV tools are substantially more expensive than Low-NA EUV, increasing fab and chip costs. They also have a smaller exposure field, which can require die stitching for large chips, complicating design and diminishing the performance advantage from reduced multipatterning.
High-NA EUV requires improved photoresists, different masks, pellicles, metrology, inspection, and computational lithography. These are not mature yet, which is why Samsung is not rushing adoption. The co-existence of SF1.4+ (an enhanced 1.4nm node using Low-NA EUV) with the 1nm-class node shows that Samsung will offer both innovative High-NA and proven Low-NA flows. This gives designers a choice but also means they must evaluate which process best fits their chip size and cost constraints.
For engineers, the extended SF2 lifespan means more time to design for a mature process, but also a longer wait for the 1.4nm node. The eventual shift to High-NA EUV at 1nm will require new design considerations, such as die stitching for large chips. The cost increase from High-NA EUV will likely be passed on to chip prices, affecting product economics. Engineers should monitor Samsung's progress with pellicles and other High-NA requirements, as these will determine the actual availability and performance of the 1nm node.
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