INFRA Signal 486
Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
A Project Oberon System variant has been retargeted from the original RISC-5 design to a RISC-V (RV32) backend using the OP2 compiler.
Engineers can now experiment with a fully documented OS, compiler, and language stack on inexpensive, widely available RISC-V hardware instead of obsolete or custom FPGA designs. The migration keeps the original memory map intact, so existing Oberon modules run unchanged, reducing porting effort.
Written by elseif from the cluster below · every claim links back to a sourceThe three things worth knowing
The OP2 compiler’s front-end/back-end split enables reuse of Oberon-07 sources while generating RV32 code.
The system’s memory map is reproduced exactly, so Kernel.Mod, Display.Mod, and Input.Mod require no modification.
Current support is limited to an RV32 emulator, with physical board deployment planned for ESP32-based development kits.
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