INFRA Signal 424
Synopsys validates a 5nm PCIe 6.0 PHY in a face-to-face 3D stack at 64 GT/s by adding through-silicon vias to an existing 2D test chip
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Synopsys published silicon results for a 5nm PCIe 6.0 PHY built into a face-to-face stacked package, achieving 64 GT/s per lane by modifying an existing 2D test chip with through-silicon vias.
Moving PCIe PHYs into a face-to-face 3D stack forces signals to route down through active silicon instead of along the die perimeter, complicating via placement and signal integrity. Synopsys' validation demonstrates that PAM4 signaling can clear bit error rate requirements in this configuration, but routing customer logic over the PHY's path remains an iterative challenge.
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Synopsys validated a 5nm PCIe 6.0 PHY in a face-to-face 3D stack at 64 GT/s per lane, achieving up to 128 GB/s across an eight-lane link.
The company modified an existing 2D test chip by adding through-silicon vias and redoing circuit design against 3D process design kits.
Face-to-face hybrid bonding forces PCIe PHYs to route signals down through vias in active silicon, creating tradeoffs between via count and signal corruption.
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