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Tenstrorrent submits GCC patches for previously unannounced Ascalon XG RISC-V core
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Tenstrorrent has released GCC compiler patches for its new Ascalon XG RISC-V CPU core variant, extending support for its high-performance RISC-V architecture in upstream toolchains.
Compiler support is a prerequisite for software adoption of new CPU cores. The patches signal Tenstrorrent’s intent to upstream its toolchain changes, reducing fragmentation for RISC-V developers targeting its hardware. Without GCC compatibility, the core remains inaccessible to most open-source projects.
Written by elseif from the cluster below · every claim links back to a sourceThe three things worth knowing
GCC patches indicate a new Ascalon XG RISC-V core variant from Tenstrorrent, distinct from the existing X model.
Upstreaming compiler support is critical for enabling software development on new CPU architectures.
The move suggests Tenstrorrent is prioritizing open-source toolchain integration for its RISC-V designs.
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