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PCIe 6.0 SSDs and controllers from Marvell, Phison, and SMI approach commercial release after delays
PCIe 6.0 SSDs and controllers are finally reaching the market, with Micron and Samsung releasing drives and Marvell, Phison, and Silicon Motion preparing their controllers.
The transition to PCIe 6.0 doubles host interface bandwidth to around 30.25 GB/s for a x4 link, but requires complex PAM4 signaling and often retimers. Engineers deploying these drives will face increased hardware complexity and slightly higher latency from Forward Error Correction.
Written by elseif from the cluster below · every claim links back to a sourceThe three things worth knowing
PCIe 6.0 doubles host interface bandwidth to approximately 30.25 GB/s for a x4 link using PAM4 signaling.
Micron and Samsung have released PCIe 6.0 SSDs, while Marvell, Phison, and Silicon Motion are preparing their controllers.
The new standard requires sophisticated DSPs, equalization, and often retimers, complicating server development and increasing latency slightly.
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PCIe 6.0 storage is moving from specification to commercial reality after years of delays. Micron and Samsung have already released PCIe 6.0 SSDs, and independent controller vendors Marvell, Phison, and Silicon Motion are preparing their platforms. This shift is supported by new host platforms like AMD's 6th Generation EPYC 'Venice' and Nvidia's Vera CPUs, which fully support the standard.
The move to PCIe 6.0 introduces significant complexity compared to previous generations. The adoption of PAM4 signaling requires sophisticated DSPs, equalization, FEC, and CRC-based retry mechanisms in controllers. Furthermore, PCIe 6.0 often requires retimers where PCIe 5.0 did not, complicating server design and increasing hardware costs.
While PCIe 6.0 doubles host interface bandwidth to around 30.25 GB/s for a x4 link, it does not improve flash operation on its own. The introduction of PAM4 and Forward Error Correction slightly increases latency. However, it delivers better bandwidth-per-watt than an equivalent 64 Gbaud NRZ implementation, which is beneficial for large data center deployments.
Marvell's Bravera SC6 (MV-SF1410) controller highlights the processing power needed for these devices, featuring 15 Arm cores including 12 Cortex-R82 cores. It is NVMe 2.2 compliant and features a PCIe 6.0 x4 host interface with 16 NAND channels. This level of complexity underscores the engineering challenges involved in bringing PCIe 6.0 storage to market.
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