INFRA Signal 509
Reverse engineering traces RTX 4090 global load instruction from warp to DRAM
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The article traces the hardware path of a global load instruction (LDG.E) on an RTX 4090 from the warp to the DRAM.
NVIDIA does not document these hardware paths to the level desired for performance optimization. Understanding this path allows developers to optimize performance by seeing the exact cost of memory operations.
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The analysis follows a global load instruction (LDG.E) on an RTX 4090 from the warp through the register file, coalescer, and L1 cache.
A single LDG.E instruction requests four bytes across 32 lanes, which the coalescer turns into four contiguous 32-byte sector requests.
The author uses timing experiments on the hardware itself to reverse engineer the undocumented details of this instruction path.
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