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Google reportedly taps AMD to design next-generation TPU — hybrid AI ASIC could integrate on-package CPU cores for reinforcement learning
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Google is reportedly collaborating with AMD to integrate AMD CPU cores into a upcoming TPU designed for reinforcement learning workloads.
The collaboration would mark AMD's first major role in a custom AI ASIC project, signaling a shift in its involvement beyond existing GPU designs. For engineers, a TPU that combines accelerator and general-purpose cores could reduce data movement and lower power consumption for RL-heavy workloads. However, the report remains speculative, and the actual scope of AMD's contribution and the resulting product are not yet confirmed.
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Google is reportedly working with AMD to develop a TPU that includes AMD CPU cores for reinforcement learning tasks.
AMD's involvement would be its first major participation in a custom AI ASIC, leveraging its CPU IP and advanced packaging expertise.
Integrating CPU cores on the same package as the TPU could shorten latency between compute units and cut power use for RL workloads.
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What the cluster adds up to.
Google is reportedly in talks with AMD to have AMD contribute CPU intellectual property for a future generation of its Tensor Processing Unit. The goal is to create a hybrid AI ASIC that places general-purpose cores on the same package as the TPU’s matrix engines. This effort targets reinforcement learning and other workloads that demand more CPU-side compute alongside accelerator operations. If realized, it would represent a new direction in Google’s TPU roadmap that explicitly couples accelerator and CPU resources.
For engineers adopting such a chip, the primary cost would be the engineering effort required to integrate AMD’s x86 cores with Google’s proprietary TPU compute dies, including interconnect design and memory hierarchy adjustments. AMD’s experience with the Instinct MI300A, which combines x86 and accelerator chiplets, provides a reference point for the required packaging technology, such as SoIC or advanced 2.5D/3D integration. However, the collaboration would also entail licensing fees or IP access costs for AMD’s CPU cores and related technologies. Power and thermal budgets would need to be rebalanced to accommodate the additional general-purpose cores on the package.
Where the approach could stop working is if the integration introduces latency or complexity that outweighs the benefits of reduced data movement, particularly for workloads that remain heavily accelerator-bound. The report remains speculative; SemiAnalysis notes that the nature of AMD’s involvement is unclear and the project may not advance beyond early discussions. If Google cannot secure the necessary packaging resources or if AMD’s CPU IP does not meet the performance targets, the plan may be abandoned. Consequently, engineers should treat the rumor as a potential future option rather than a confirmed product roadmap.
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