Performance impact of Alignment

Alignment is defined as an address being a multiple of a given size, typically a power of two. For scalar accesses the element size determines alignment, but a SIMD vector of many elements requires the address to be a multiple of the whole vector's byte size. Consequently, code that simply iterates over an array may need extra handling to guarantee that vector loads start on a suitably aligned boundary.

Some legacy CPUs only permit aligned memory operations; a misaligned address can cause a fault or silently truncate the address. Because of this, compilers must be able to prove that a given address meets the platform's alignment constraints before they can emit vector instructions. Developers may need to add explicit alignment checks or restructure data layouts to satisfy these strict requirements.

Modern processors generally support unaligned loads and stores, and the performance penalty is often negligible when the access stays within a single cache line. The critical case is when an access straddles a cache-line boundary, at which point the hardware splits the operation into two separate memory transactions. This split adds extra work in the memory subsystem and can noticeably slow down execution, especially if many such accesses occur.

The overall impact of misaligned accesses depends on how frequently loads or stores cross cache lines and whether the program is already limited by memory bandwidth. If only a few accesses are split and the code is compute-bound, the slowdown may be minor. However, in memory-bound kernels where most accesses are split, the effective throughput can drop dramatically, potentially halving performance.

Practical experimentation shows the effect clearly: a simple benchmark that loads a vector from an array with an offset and stores it back demonstrates measurable slowdown when the offset causes cache-line crossing. Engineers should therefore consider padding arrays, aligning allocations, or using explicit offsets that keep vector accesses within cache lines to preserve the expected speedup from SIMD vectorization.