INFRA Signal 409
RISC-V RVA23 shows 24% smaller dynamic instruction fetch than ARMv9 in compiler workload test
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A small experiment comparing RISC-V RVA23 and ARMv9 in a C compiler workload found RISC-V fetched fewer bytes but executed more instructions than ARMv9
Engineers selecting an ISA for embedded or low-power designs must trade off instruction density against decode complexity. This experiment quantifies the byte-fetch advantage of RISC-V’s compressed encoding, but also shows ARMv9’s simpler dynamic instruction stream. Neither ISA dominates on all metrics, so the choice remains workload-dependent.
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RISC-V RVA23 binaries were 18 % smaller statically and fetched 24 % fewer bytes dynamically than ARMv9 in the test
ARMv9 executed 6.5 % fewer instructions than RISC-V, but some of those instructions expanded into two micro-ops
After micro-op expansion, both ISAs fed roughly the same number of micro-ops to the backend, with RISC-V slightly ahead on GCC
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The experiment used a single C compiler (chibicc) compiling itself as a workload. All files were merged into one translation unit and compiled statically with both clang and GCC at -O3. SIMD and vector instructions were explicitly disabled to isolate the base ISA comparison. The test measured static binary size, dynamic instruction fetch size, instruction count, micro-op count, and simulated execution time under QEMU and GEM5.
RISC-V RVA23 showed a clear advantage in instruction density. Static binaries were 18 % smaller than ARMv9, and dynamic instruction fetch was 24 % smaller. This stems from RISC-V’s compressed 16-bit encoding for common instructions. ARMv9, in contrast, executed 6.5 % fewer instructions, but its more complex addressing modes caused some instructions to expand into two micro-ops, erasing the instruction-count advantage.
After micro-op expansion, the two ISAs converged. Clang-generated code for both ISAs produced roughly the same number of micro-ops, while GCC-generated RISC-V code produced slightly fewer. GEM5 simulation suggested RISC-V executed faster, but the author cautioned that the simulator’s micro-architectural models may not reflect what a real design team would achieve with the same budget.
The difference between RVA22 and RVA23 was negligible in this workload. RVA23’s new extensions (Zcb, Zfa, Zicond) did not significantly alter instruction count or fetch size. The experiment’s narrow scope, one compiler, one workload, no SIMD, limits its generalizability, but it provides concrete numbers for engineers evaluating ISA trade-offs in scalar code.
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