PERFORMANCE Signal 377
Samsung targets HBM5 to deliver 4 TB/s per stack, doubling HBM4E bandwidth and improving power efficiency by 20%
↗
Samsung announced that HBM5 aims to double the bandwidth of HBM4E to 4 TB/s per stack and improve performance per watt by 20% by the late 2020s.
Doubling bandwidth in a single generation requires either doubling the per-pin data transfer rate to 24 GT/s or widening the interface to 4,096 bits, both of which present significant engineering challenges for PHY and packaging complexity. If achieved, future AI accelerators packing 20 to 24 stacks could reach 80 to 96 TB/s of memory bandwidth. However, the exact HBM5 specifications remain speculative until JEDEC finalizes them.
Written by elseif from the cluster below · every claim links back to a sourceThe three things worth knowing
Samsung targets HBM5 to deliver 4 TB/s of bandwidth per stack, doubling the expected HBM4E performance.
The specification could involve doubling the interface width to 4,096 bits or increasing the per-pin data transfer rate to 24 GT/s.
HBM5 also aims for a 20% improvement in performance per watt compared to HBM4E.
THE CLUSTER